The present invention relates generally to the field of hardware performance data, and more particularly to hardware performance data collection.
Many modern day computer processors comprise a performance monitoring unit (PMU) for gathering information about workload characteristics and computer hardware performance. PMUs are often implemented as counters which can be configured to count certain hardware events that correspond to performance metrics of the given processor. Some examples of hardware events can be, but are not limited to, instruction cycles, cache hits, cache misses and branch misses. Hardware event counters which track hardware performance data can periodically write the collected data into memory, consuming memory bandwidth in the process, where the data may be analyzed by monitoring software for gathering insights about hardware performance.